library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use WORK.constants.all;

entity CORE_RIGHT is
	port (
		-- Systesm signals
		clk			: in std_logic;
		
		-- Input signals coming from Core_Left
		shift		:	in std_logic;
		capture		:	in std_logic;
		update		:	in std_logic;
		gwen		:	in std_logic;
		gw_reset		:	in std_logic;
		hw_and_sw_reset : in std_logic;
		tdi			:	in std_logic;
		-- Output signal going to Core_Left
		tdo			:	out std_logic
	);
end CORE_RIGHT;

architecture RTL of CORE_RIGHT is 

component Gateway is
    Port ( tdi : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           shift : in  STD_LOGIC;
           update : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           wsoi : in  STD_LOGIC;
           sel : out  STD_LOGIC;
           wsio : out  STD_LOGIC;
           tdo : out  STD_LOGIC);
end component;

COMPONENT IJTAG
	PORT(
		tdi : IN  std_logic;
		sele : IN  std_logic;
		shift : IN  std_logic;
		update : IN  std_logic;
		capture : IN  std_logic;
		reset : IN  std_logic;
		clk : IN  std_logic;
		tdo : OUT  std_logic
	  );
END COMPONENT;

signal s_shift, s_update : std_logic;
signal sel, wsoi : std_logic_vector(N_GW downto 1);
signal tdinn : std_logic_vector(N_GW downto 2);
signal wsio : std_logic_vector(N_GW downto 1);
signal compio1 : std_logic_vector(2 downto 1);
signal compio2 : std_logic_vector(3 downto 1);
signal compio3 : std_logic_vector(4 downto 1);
signal reset : std_logic;
begin

	-- generation of specialized control signals
	reset <= hw_and_sw_reset or not(gw_reset);
	s_shift	<= shift and gwen;
	s_update	<= update and gwen;

----------------------------------------------------------------------
--- creation and chaining of the 3 gateways present on the system ----
--- This chain has 4 IJTAG elements.                              ----
----------------------------------------------------------------------	
gw0: Gateway
	port map(tdi, clk, s_shift, s_update, reset, wsoi(1), sel(1), wsio(1), tdinn(2));
	
gw1: Gateway
	port map(tdinn(2), clk, s_shift, s_update, reset, wsoi(2), sel(2), wsio(2), tdinn(3));
	
gw2: Gateway
	port map(tdinn(3), clk, s_shift, s_update, reset, wsoi(3), sel(3), wsio(3), tdo);


-- Automatic generation of the chain of gateways and IJTAG components
-- In the structure compio, for each gateway a structure of 6 elements is instantiated
-- The first entry of the array is the input from the previous gateway, the last entry is
-- the output to the next gateway, and the other values are the outputs of the IJTAG components

--chains : for i in 1 to N_GW generate

--	compio(i)(0) <= wsio(i);
--	compio(i)(0) <= tdinn(i);
-- The first gateway will have 3 elements, the second 4 etc.
--	chain: for n in 0 to (1+i) generate
--			comp: IJTAG 
--			port map(compio(i)(n), sel(i), shift, update, capture, hw_and_sw_reset, clk, compio(i)(n+1));
--	end generate;

--	wsoi(i) <= compio(i)(1+i+1);
--end generate;


----------------------------------------------------------------------
--- creation of the chain connected to the first gateway composed. ---
--- This chain has 3 IJTAG elements.                               ---
----------------------------------------------------------------------
comp10 : IJTAG
   port map(wsio(1), sel(1), shift, update, capture, hw_and_sw_reset, clk, compio1(1));
   
comp11 : IJTAG
   port map(compio1(1), sel(1), shift, update, capture, hw_and_sw_reset, clk, compio1(2));

comp12 : IJTAG
   port map(compio1(2), sel(1), shift, update, capture, hw_and_sw_reset, clk, wsoi(1));	
	
	
-----------------------------------------------------------------------
--- creation of the chain connected to the second gateway composed. ---
--- This chain has 4 IJTAG elements.                                ---
-----------------------------------------------------------------------
comp20 : IJTAG
   port map(wsio(2), sel(2), shift, update, capture, hw_and_sw_reset, clk, compio2(1));
   
comp21 : IJTAG
   port map(compio2(1), sel(2), shift, update, capture, hw_and_sw_reset, clk, compio2(2));

comp22 : IJTAG
   port map(compio2(2), sel(2), shift, update, capture, hw_and_sw_reset, clk, compio2(3));		
	
comp23 : IJTAG
   port map(compio2(3), sel(2), shift, update, capture, hw_and_sw_reset, clk, wsoi(2));	
	

----------------------------------------------------------------------
--- creation of the chain connected to the third gateway composed. ---
--- This chain has 4 IJTAG elements.                               ---
----------------------------------------------------------------------
comp30 : IJTAG
   port map(wsio(3), sel(3), shift, update, capture, hw_and_sw_reset, clk, compio3(1));
   
comp31 : IJTAG
   port map(compio3(1), sel(3), shift, update, capture, hw_and_sw_reset, clk, compio3(2));

comp32 : IJTAG
   port map(compio3(2), sel(3), shift, update, capture, hw_and_sw_reset, clk, compio3(3));		
	
comp33 : IJTAG
   port map(compio3(3), sel(3), shift, update, capture, hw_and_sw_reset, clk, compio3(4));	
	
comp34 : IJTAG
   port map(compio3(4), sel(3), shift, update, capture, hw_and_sw_reset, clk, wsoi(3));
end;
